1. Technical Field
The invention is related to digital communication devices and in particular to a receive digital phase lock loop.
2. Background Art
Digital communications such as those provided in a wide area network (WAN) or local area network (LAN) of personal computers (for example) are constantly being improved to operate at higher data rates. For example, there is considerable interest in developing networks capable of operating at a clock frequency of 10 MHz, corresponding to a pulse width of 50 nanoseconds (nS). Preferably, the data transmitted on the network is Manchester encoded. The problem with such a high data rate (narrow pulse width) is that the system is particularly susceptible to failure due to distortion of the data stream inherent in any transmission medium, such as cables running between offices in a large building for example. The speed at which the data-containing signal travels through the cable is affected by a number of things including stray capacitances that can vary depending upon surrounding conditions. Such changes cause the signal""s speed to vary. Such variations cause jitter in the received signal, in which the time between successive pulses observed at a receiving point in the network fluctuates, causing the apparent position of each pulse to drift. If this drift becomes excessive, the receiving device cannot maintain synchronization between the incoming data stream and its own clock, leading to complete loss of the received signal. For a typical cable, the drift induced by jitter can be exceed 10 nS and can be as great as 13.5 nS. For older systems that operate at lower frequencies (and therefore larger pulse widths), this does not pose a significant problem. However, a 13.5 nS drift in a high-speed system in which the pulse width is only 50 nS, for example, often causes loss of synchronization and therefore failure.
Typically, a digital phase lock loop (PLL) operating at a clock rate many times the frequency of the incoming data maintains synchronization between the incoming data and the receiver, so that the receiver takes only a narrow sample of each pulse near the center of the pulse or at least well away from either edge of the pulse. The time at which each data sample is taken (the data sample point) is controlled by the PLL. The goal of the phase lock loop is to follow the drift in the received signal so as to keep the data sample point in the middle of each successive pulse. I previously developed a high speed digital PLL having a phase error counter and an edge counter. The edge counter counts the number of edges and indicates when the phase lock loop should update its data sample point. The phase error counter tracks the phase of the incoming signal relative to the PLL""s current sample data point, and periodically updates this point. At the update time, the phase error counter polarity indicates whether to advance or retard the data sample point by one clock. Upon making this correction, both the phase error counter and the edge counter are cleared, and the process is restarted.
I found that the foregoing architecture, when applied to data having a frequency of 10 MHz, was inadequate to withstand jitter of well over 10 nS, e.g., jitter of 13.5 nS. That is, the architecture was susceptible to synchronization loss in the presence of jitter of 13.5 nS. Since this amount of jitter can be expected in many applications, it is a goal of the present invention to improve this architecture to the point that it can reliably maintain synchronization of 10 MHz data in the presence of 13.5 nS jitter.
One problem with the foregoing architecture is that the selection of the time between updates necessarily involves a tradeoff between two constraints. One constraint is that each block of data is preceded by a preamble of successive uniform pulses, typically about 56 pulses, during which synchronization must be attained before the actual data stream begins. This requirement demands minimizing the time between updates so that the PLL achieves synchronization as quickly as possible. The other constraint is that the PLL be stable and not susceptible to a temporary phase deviation in the incoming data. This latter requirement demands maximizing the time between updates so that the PLL is fairly insensitive to temporary phase deviations. Thus, it does not appear both requirements can be met together. It is therefore another goal of the invention to establish synchronization very quicklyxe2x80x94before the end of the preamblexe2x80x94without sacrificing stability of the PLL.
It is a discovery of the invention that one factor contributing to synchronization loss in the presence of jitter is the one-clock uncertainty in the position of the pulse center point. This makes the choice between the two samples straddling the middle of each pulse ambiguous. This ambiguity follows from the fact that the resolution of the PLL is no better than one clock period.
This limitation is overcome in the invention by resolving the ambiguity between the two samples nominally centered about the pulse center point. This is achieved by intelligently choosing between the two samples nearest the pulse center by exploiting information from the phase error. Specifically, the choice is made depending upon the sign of the phase error. The result is that the margin of error of the PLL is improved by a half clock period, since on the average the choice between each one of the two samples represents half of the total one-clock resolution limit of the system.
Accordingly, the invention is embodied in a digital phase lock loop (PLL) having phase error-directed sample selection about a pulse center point, the PLL having an internal PLL clock. The PLL includes a data signal input at which an incoming data signal is received, the data signal including successive pulses having a characteristic pulse edge rate, the internal PLL clock having a clock rate about M times the pulse edge rate to define M successive samples of each one of the successive pulses. A state machine of the PLL has an internal cyclic count of modulus M incremented in synchronism with the internal PLL clock, corresponding to M successive samples of each one of the successive pulses. The internal cyclic count includes (a) a predetermined center count value tending to coincide with center regions of the successive pulses, and (b) a predetermined edge count value offset from the center count value by approximately one half of one pulse width of the successive pulses and tending to coincide with edges of the successive pulses. The PLL includes sampling logic connected to receive the data signal and having a sampling control input connected to an output of the state machine, the sampling logic being capable of selecting a current one of the M successive samples whenever the internal count reaches the predetermined center count value. A phase error detector, having one input for receiving the internal count from the state machine and an edge input responsive to receipt of the edges of the successive pulses, produces a correction output signal corresponding to a phase difference between the time of occurrence of at least one of the successive edges and the time of occurrence of the edge count value of the internal count. The state machine further includes a control input for advancing or retarding the internal count, the control input receiving at least a portion of the correction output signal. The PLL includes a selective delay element connected between the data signal input and the sampling logic and having a select input connected to receive a sign bit of the correction output signal corresponding to the sign of the phase difference, the selective delay element capable of interposing a delay of one period of the internal PLL clock depending upon the sign bit, whereby to select between one of two samples near the center of a current pulse.